Understanding the CPU Instruction Cycle

Phase 1: The Fetch Stage

The cycle begins with the Fetch stage. The CPU does not "know" what to do until it retrieves an instruction from the system memory.

1. The address stored in the Program Counter (PC) is copied to the Memory Address Register (MAR).
2. The CPU sends a signal to the memory to read the data at that specific address.
3. The instruction located at that address is transferred from memory into the Memory Data Register (MDR).
4. The instruction is then moved from the MDR into the Instruction Register (IR) for processing.
5. Crucially, the Program Counter (PC) is incremented (e.g., $PC \leftarrow PC + 1$) so that it points to the next instruction in the sequence, preparing for the next cycle.

Exam Tip: Remember that the PC is updated during the fetch phase, not after execution. This ensures that even if the current instruction causes an error, the CPU has already "marked its place" for the next step.

Phase 2: The Decode Stage

Once the instruction is safely inside the Instruction Register (IR), the Decode stage begins. This is where the Control Unit (CU) takes over.

The instruction is a string of binary digits (bits). The Control Unit must interpret these bits to determine two things:

1. The Opcode (Operation Code): What action is being requested? (e.g., ADD, LOAD, JUMP).
2. The Operands: What data is being acted upon? This could be a constant value, a register number, or a memory address.

During this phase, the Control Unit activates specific internal pathways (control signals) that prepare the ALU or the memory interface for the upcoming operation.

Phase 3: Execute and Writeback

The final stages involve the actual "work" of the instruction.

Execution

In the Execute stage, the CPU carries out the command identified during the decode phase. If the instruction is an arithmetic operation, the ALU is engaged. For example, if the instruction is ADD R1, R2, the ALU will take the values from registers R1 and R2 and calculate their sum.

Writeback

The Writeback stage is the final step where the results of the execution are stored. This might involve:

• Writing a calculated value back into a specific register.
• Writing a result back to a specific location in the main memory (RAM).

Without the writeback stage, the results of our computations would be lost as soon as the next instruction began.

Modern Complexity: Micro-operations (uops)

In modern, high-performance processors, the instruction cycle is significantly more complex than the simple four-step model described above. Modern CPUs often use Micro-operations (uops).

Instead of executing one massive, complex instruction directly, the hardware breaks it down into several much smaller, simpler "micro-ops" that can be executed very quickly. This allows for advanced techniques like:

• Pipelining: Overlapping different stages of different instructions (fetching instruction B while executing instruction A).
• Out-of-Order Execution: Executing instructions as soon as their required data is available, rather than strictly following the program order, to keep the ALU busy.

By decomposing instructions into uops, modern architectures can achieve much higher throughput, effectively performing many "mini-cycles" within a single clock cycle of the main processor.